Many conventional computer systems suffer from low channel utilization. This is described below with reference to FIGS. 1 and 2. Note that, in the drawings, like reference numbers (with, perhaps, different alphabetic suffixes) indicate identical or functionally similar elements. In this patent document, when generically describing an element, the element's reference number alone is used. When specifically describing a particular element, the element's reference number and alphabetic suffix is used.
FIG. 1 is a block diagram of a conventional computer system 102. The computer system 102 includes a central processing unit (CPU) 108, a random access memory (RAM) 110, an input/output processor (IOP) 118, a channel subsystem 106 having multiple channels 128, a switch 140, multiple control units (CUs) 151, 152, and multiple peripheral devices 161, 162. The general structure and operation of these components are well known.
For clarity purposes, only one device 161, 162 is shown connected to each CU 151, 152 in FIGS. 1, 2, 3A, and 3B. Often, however, multiple devices 161, 162 are connected to each CU 151, 152.
The IOP 118, the channel subsystem 106, and the switch 140 are collectively called an input/output (IO) subsystem 104.
The computer system 102 operates according to application programs 170, an operating system 172, access methods (or device drivers) 174, and microcode 176. The general structure and operation of the application programs 170, the operating system 172, the access methods 174, and the microcode 176 are well known.
The devices 161, 162 communicate with the CPU 108 and the RAM 110 via physical paths. As shown in FIG. 1, a limited number of physical paths exist between the devices 162 and the CPU 108 (or equivalently, between the devices 162 and the RAM 110). Specifically, in this example, there are three physical paths between the devices 162 and the CPU 108. These physical paths include the channels 128H, 128I, 128J, the switch 140, and the CUs 152. For example, one of the physical paths from the device 162A and the CPU 108 includes the channel 128I, the switch 140, and the CU 152A.
Ideally, the devices 162 and the CPU 108 may use all of the physical paths to communicate.
In the conventional computer system 102, however, the devices 162 are not permitted to use all of the physical paths. This is true because of the architecture, implementation, and initialization limits placed on the devices 162, which restrict the use of all the channels 128H, 128I and 128J. For example, during initialization of the computer system 102, the IO subsystem 104 may be configured such that the devices 162 may use only the channels 128H and 128I. Consequently, only two physical paths would be available for communication between the devices 162 and the CPU 108--the physical paths involving the channels 128H and 128I.
FIG. 2 illustrates the conventional computer system 102 in greater detail (for clarity, FIG. 2 does not show the CPU 108, the RAM 110, or the IOP 118).
In the conventional computer system 102, a subchannel 202A, 202B, 202C, 202D is associated with each device 161, 162A, 162B, 162C, respectively. The subchannels 202 are tables which are stored in the RAM 110 or in an IOP-dedicated memory (not shown in FIG. 1). The subchannels 202 contain channel path identifiers (CHPIDs) 204.
The CHPIDs 204 are used to identify (that is, to address) the channels 128. For example, the CHPID 204A identifies the channel 128A. The CHPID 204I identifies the channel 128I. (In this patent document, the following convention is used: the CHPID 204.times. identifies the channel 128.times..)
A CHPID 204 may identify only one channel 128. However, multiple subchannels 202 may identify the same channel 128. For example, the CHPIDs 204I in the subchannels 202B, 202C, 202D identify the channel 128I.
The CHPIDs 204 also are used to identify (that is, to address) physical paths between the devices 161, 162 and the CPU 108. For example, the subchannel 202B contains the CHPIDs 204H, 204I which identify the channels 128H, 128I, respectively. The subchannel 202B is associated with the device 162A. Thus, the CHPIDs 204H, 204I identify two physical paths between the device 162A and the CPU 108--the physical paths including the channels 128H, 128I, the switch 140, and the CU 152A. Generally, multiple switches 140 may exist.
The IOP 118 references the subchannels 202 to access the devices 161, 162. Specifically, the IOP 118 references the CHPIDs 204 in the subchannels 202 to determine the channels 128 and the physical paths associated with the devices 161, 162. The IOP 118 then uses the determined physical paths to access the devices 161, 162 (that is, to allow communication between the devices 161, 162 and the CPU 108). Thus, the IOP 118 references the subchannels 202 to directly address the channels 128.
The subchannels 202 contain addresses of the devices 162 within their CUs 152. Link addresses of control unit interfaces are associated with the CHPIDs 204. The link addresses are the addresses to which the switch 140 makes its connections.
As shown in FIG. 2, there are five possible physical paths between the devices 162 and the CPU 108. These five possible physical paths include the channels 128F, 128G, 128H, 128I, 128J (note that both the devices 162 and the channels 128F, 128G, 128H, 128I, 128J are connected to the switch 140). As noted above, however, the devices 162 are not permitted to use all of the physical paths. This is true because of the architecture, implementation, and initialization limits placed on the devices 162, which restrict the use of all the channels 128F, 128G, 128H, 128I and 128J. The devices 162 are not permitted to use all of the channels 128F, 128G, 128H, 128I, 128J because the subchannels 202 can store only a limited number of the CHPIDs 204.
Referring to the subchannels 202B, 202C, 202D in FIG. 2, the IO subsystem 104 is configured such that the devices 162 may use only the channels 128H and 128I. Consequently, only two physical paths are available for communication between the devices 162 and the CPU 108--the physical paths involving the channels 128H and 128I.
Because the devices 162 are not permitted to use all of the physical paths, the devices 162 may not be able to communicate with the CPU 108. For example, if the devices 162A, 162B are communicating over the channels 128H, 128I, then a physical path does not remain for the device 162C. Therefore, the device 162C cannot communicate with the CPU 108. This is true, even though the channels 128F, 128G, 128J may be idle.
Therefore, the conventional computer system 102 results in one or more of the devices 162 waiting to communicate on its assigned channels 128 while one or more unassigned channels 128 are often idle. Devices 162 waiting to communicate result in lower system performance and the idle channels 128 result in low channel utilization.
In a prior solution to the above problem, the subchannels 202 are modified to store additional CHPIDs 204. In FIG. 2, the subchannels 202 store four CHPIDs 204. Therefore, a maximum of four physical paths are available for each of the devices 161, 162. According to the prior solution, the subchannels 202 are modified to store eight CHPIDs 204. Therefore, a maximum of eight physical paths are available for each of the devices 161, 162.
However, the prior solution is wasteful because many devices 161, 162 require less than eight physical paths. For example, the device 161 is associated with two dedicated physical paths and thus requires only two CHPIDs 204A, 204E. However, the prior solution requires that all of the subchannels 202 be modified to store eight CHPIDs 204.
Therefore, the prior solution is flawed because it inefficiently consumes the RAM 108 and IOP-dedicated memory required to store the subchannels 202.
Further, the prior solution is flawed because it requires significant modifications to existing computer systems 102. For example, the subchannels 202 in the computer system 102 must be modified to store eight CHPIDs 204 in order to implement the prior solution.
Thus, a system and method for addressing channels are required which result in high channel utilization without inefficiently consuming memory and without requiring significant system modifications.